来源：https://www.synopsys.com/glossary/what-is-parasitic-extraction.html
In electronic design automation (EDA), parasitic extraction (PEX) is calculation of the parasitic effects in both the designed devices and the required wiring interconnects of an electronic circuit: parasitic capacitances, parasitic resistances and parasitic inductances, commonly called parasitic devices, parasitic components, or simply parasitics.
在电子设计自动化(EDA)中，寄生提取(PEX)是计算电子电路的设计器件和所需布线互连线中的寄生效应：寄生电容、寄生电阻和寄生电感，通常称为寄生器件、寄生元件或简单的寄生元件。
The major purpose of parasitic extraction is to create an accurate analog model of the circuit, so that detailed simulations can emulate actual digital and analog circuit responses. Digital circuit responses are often used to populate databases for signal delay and loading calculation such as:
Timing analysis
Power analysis
Circuit simulation
Signal integrity analysis
寄生提取的主要目的是建立一个精确的电路模拟模型，使详细的模拟能够模拟实际的数字和模拟电路响应。 数字电路响应通常用于填充数据库，用于信号延迟和加载计算，如：
时序分析
电源分析
电路模拟
信号完整性分析
Analog circuits are often run in detailed test benches to indicate if the extra extracted parasitics will still allow the designed circuit to function.
模拟电路通常在详细的测试中运行表面额外提取的寄生电路是否仍然允许设计的电路正常工作。
注释：Parasitic capacitance between two neighboring layers of metal
两个相邻金属层之间的寄生电容
Parasitic capacitance between metals of the same layer
寄生电容存在于相同层的金属之间
Different categories of Parasitics
不同类别的寄生效应
On a typical semiconductor die you can categorize the parasitics in 3 categories:
在典型的半导体晶粒上，您可以将寄生在三个类别中：
Front-end of the Line (FEOL). Parasitics associated with the semiconductor devices.
前道工艺（FEOL）。寄生效应与半导体器件联系
Middle-end of the Line (MEOL). Parasitics associated with the contacts on semiconductor devices.、
中道制成工艺（MEOL）。寄生效应与半导体器件的连接点有联系
Back-end of the Line (BEOL). Parasitics associated with the interconnect layers.
后道工艺（BEOL）。寄生效应与互连层有关
How does Parasitic Extraction Work?
寄生效应提取是如何工作的。
There are two types of engines which can be used for parasitic extraction:
这里有两种经典的驱动策略被使用在寄生参数提取：
Fields Solver Based. In this method, the PEX engine solves Maxwell’s equations to calculate the parasitic R, C, L or K. This method is referred to as 3D extraction. It is a higher accuracy method than the rule-based method, but also takes more processing power and is not used for full-chip extraction. Within the field solver category, you could have finite element or random walk algorithm being employed – tradeoff being processing time vs. accuracy, finite element algorithm being more accurate.
基于场解算器。在这种方法中，PEX引擎通过求解麦克斯韦方程来计算寄生电阻、电容、电感或K。这种方法称为3D提取。它是一种比基于规则的方法精度更高的方法，但也需要更多的处理能力，不用于全芯片提取。在“场解算器”类别中，可以使用有限元或随机游走算法--在处理时间与精度之间进行权衡，有限元算法更精确。
工艺规范
设计布局
参数提取。。。。
Rule Based. In this method, the PEX engine uses a look up table to calculate the parasitic R or C. This method is referred to as 2D or 2.5D extraction. It can support full-chip extraction.
规则提取算法。在这种方法中，PEX引擎使用一个查找表来计算寄生R或C。这种方法称为2D或2.5D提取。支持全芯片提取。
工艺规范 模型校准 提取规则 基于规则算法的寄生参数提取 提取网络。。
What solutions does Synopsys offer for Parasitic Extraction?
Synopsys为寄生参数提取提供了哪些解决方案？
Synopsys offers parasitic extraction solutions for both digital and custom design environments:
Synopsys为数字和定制设计环境提供寄生提取解决方案：
StarRC™ solution is the EDA industry’s gold standard for parasitic extraction. A key component of Synopsys Design Platform, it provides a silicon accurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal. memory IC and 3DIC designs. StarRC offers modeling of physical effects for advanced process technologies, including FinFET technologies at 16 nm, 14 nm, 10 nm, 7 nm, 5 nm and beyond. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows along with debugging capability delivers unmatched ease-of-use and productivity to speed design closure and signoff verification. StarRC comes with in-built field solver Rapid3D™, which can serve as a reference or provide higher accuracy measurements. 2.5D and 3D-IC extraction is also supported by StarRC.
Starc™ 解决方案是EDA行业寄生提取的黄金标准。作为Synopsys设计平台的关键组件，它为SoC、定制数字、模拟/混合信号提供了一种硅精度高性能的提取解决方案。存储器IC和3DIC设计。StarRC为先进工艺技术提供物理效应建模，包括16 nm、14 nm、10 nm、7 nm、5 nm及以上的FinFET技术。它与行业标准的数字和定制实现系统、定时、信号完整性、电源、物理验证和电路模拟流程以及调试功能无缝集成，提供无与伦比的易用性和生产率，以加快设计关闭和签核验证。StarRC配备了内置的场解算器Rapid3D™，可作为参考或提供更高精度的测量。StarRC还支持2.5D和3D-IC提取。
QuickCap NX is the golden extraction reference tool based on high accuracy 3D Field Solver which is well suited for advanced 14nm FinFET and beyond process technologies. Embedded 3D device visualizer makes it ideal for process exploration. High accuracy extraction, reference tool to rule based extractor, standard cell characterization, memory cell characterization and enhancing PDK quality are some of the key applications served by QuickCap NX.
QuickCap NX是基于高精度3D场解算器的黄金提取参考工具，非常适合先进的14nm FinFET和其他工艺技术。嵌入三维器件可视化工具使其成为过程探索的理想选择。高精度提取、基于规则的抽取器的参考工具、标准单元表征、存储单元表征和增强PDK质量是QuickCap NX服务的一些关键应用。
Raphael is the gold standard, 2D and 3D resistance, capacitance and inductance extraction tool for optimizing on-chip parasitic for multi-level interconnect structures in small cells. As a reference field solver, Raphael provides the most accurate parasitic models in the industry. Trusted by major foundries, interconnect parasitics generated by Raphael are included as part of their design reference guide.
Raphael是一个黄金标准、二维和三维电阻、电容和电感提取工具，用于优化小单元中多层互连结构的片上寄生。作为一个参考场解算器，Raphael提供了业界最精确的寄生模型。受主要铸造厂的信任，由Raphael产生的互连寄生作为其设计参考指南的一部分。
