StarRC Solution
StarRC 解决方案
Semiconductor process technology has been continually scaling down for the past four decades and the trend continues.
半导体工艺技术一直在缩小已经持续了四十多年，这个趋势仍在继续。
Shrinking process geometries, combined with the use of new device structures like FinFETs and an increasing number of metal layers at each new process node, are introducing millions of new parasitic effects in designs.
几何预缩工序，结合使用新的器件结构，如FinFET和在每个新的工艺节点上增加金属层的数量，在设计中引入了数百万个新的寄生效应。
In addition, soaring design sizes and complexities are increasing the sensitivity of circuits to parasitics due to the increasing impact on signal timing, noise and power.
此外，由于对信号定时、噪声和功率的影响越来越大，飙升的设计尺寸和复杂性增加了电路对寄生电路的灵敏度。
To ensure a successful silicon design and meet tapeout schedules, IC designers need an advanced parasitic extraction solution that delivers signoff accuracy and increased designer productivity.
为了确保成功的硅设计和满足磁带输出计划（tapeout:原意是指“下线”，指的是集成电路（IC）或印刷电路板（PCB）设计的最后步骤，也就是送交制造 ），IC设计人员需要一种先进的寄生提取解决方案，精度和提高设计人员的生产力。
Furthermore, they need a solution that is versatile enough to manage the full design spectrum from custom digital, analog/mixed-signal (AMS) to full chip memory and SoC designs.
此外，他们需要一个足够通用的解决方案来管理从自定义数字、模拟/混合信号(AMS)到全芯片存储器和SOC设计的完整设计频谱。
Synopsys’ StarRC is the proven high-accuracy and high-performance parasitic extraction solution for digital and custom IC implementation and signoff verification (Figure 1).
新思科技的StarRC软件为数字和自定义IC实施和signoff验证提供了高进度高性能的寄生参数提取解决方案
Trusted by hundreds of semiconductor companies and used in thousands of production designs, StarRC provides sub-femtofarad-accurate technology for design at advanced process technologies.
在数百家半导体公司的信任下，在数千种生产设计中使用，StarRC为先进工艺技术的设计提供了高精度的技术。
It achieves its high accuracy by performing detailed modeling of device and interconnect parasitic effects in nanometer process technologies.
在纳米工艺技术中，通过对器件的详细建模和互连寄生效应，实现了其高精度。
The advanced modeling and accuracy is complemented with the embedded Rapid3D field solver technology for circuits that require even higher accuracy.
先进的建模和精度与嵌入式快速三维场求解器技术相补充，用于需要更高精度的电路。
StarRC delivers industry-leading performance and capacity for users’ gate-level and transistor-level extraction needs.
StarRC提供行业领先的性能和容量，为用户的门级和晶体管级提取需求。
StarRC’s multi-core distributed processing technology delivers excellent scalability for efficient utilization of available hardware,and its simultaneous multi-corner extraction (SMC) feature allows the increasing number of extraction corners required for analysis to be processed within a single run with significantly reduced runtime and disk usage.
StarRC的多核分布式处理技术为有效利用可用硬件提供了极好的可伸缩性，其同时多角提取(SMC)特性允许在一次运行中处理分析所需的提取角的数量增加，大大减少了运行时和磁盘的使用。
Its seamless integration with Synopsys’ place-and-route IC Compiler™ and IC Compiler II physical implementation, gold standard PrimeTime® static timing analysis (STA) signoff, Galaxy Custom Designer® mixed-signal implementation, IC Validator physical verification, CustomSim™ circuit simulation and other third-party implementation and signoff tools enables users to significantly accelerate their design implementation and verification.
StarRC完美整合了。。。。。。.软件使用户能够显著加快其设计实现和验证。
Benefits
优势
1.Foundry gold standard for extraction accuracy with broadest qualification and adoption
黄金标准的提取精度与最广泛的资格和采用
2.Leader in advanced modeling, including FinFET and color-aware multi-patterning at 10nm/7nm and beyond.
高级建模的领先者，包括FinFET和颜色感知的多图案在10nm/7nm和更高。
3.High performance and capacity for gate and transistor-level extraction, enabled by multi-core distributed processing and simultaneous multi-corner extraction
高性能和容量的门和晶体管级提取，启用多核分布式处理和同时多角提取
4.Tightly integrated with industry leading IC Compiler II and PrimeTime solutions for faster full-flow ECO turn-around time
紧密结合行业领先的IC编译器II和Prime时间解决方案，以更快的全流ECO周转时间
5.Unified Rapid3D fast field solver for critical net, IP, and custom circuit extraction
统一临界网、IP和自定义电路提取的统一Rapid3D快速场求解器
6.Advanced netlist reduction features for faster simulation turn-around time
先进的Netlist减少功能，以更快的模拟周转时间
7.Inductance extraction for high frequency digital RLC clock net analysis
高频数字RLC时钟网分析的电感提取
8.3D-IC extraction solution for interposer and stacked die technologies
3D-IC提取解决方案的干涉和堆叠模具技术
9. Integration with IC Validator physical verification, CustomSim circuit simulation, Galaxy Custom Designer and other third party implementation and custom design solutions for increased designer productivity
集成IC验证器物理验证、自定义SIM电路仿真、Galaxy自定义设计器等第三方实现和自定义设计解决方案，提高设计人员的生产力
