when considering the set of operations a given processor provides, we need to remember that the choice represents a complex tradeoff:
The set of operations a processor provides represents a tradeoff among the cost of the hardware, the convenience for a programmer, and engineering considerations such as power consumption.

Variable-Length Vs. Fixed-Length Instructions
Programmers expect variable-length instructions because software usually allocates space according to the size of each object .
From a hardware point of view, however, variable-length instructions require complex hardware to fetch and decode.
By comparison, fixed-length instructions require less complex hardware. Fixed-length instructions allow processor hardware to operate at higher speed because the hardware can compute the location of the next instruction easily.

Unused field
When a fixed-length instruction set is employed, some instructions contain extra fields that the hardware ignores. The unused fields should be viewed as part of a hardware optimization, not as an indication of a poor design.

General-Purpose Registers
A register is a small, high-speed hardware storage device found in a processor.
fixed size (e.g., 32 or 64 bits) and supports two basic operations: fetch and store.

Registers can operate in a variety of roles, including as an** instruction pointer** (also called a program counter) that gives the address of the next instruction to execute.

32 registers:
A processor usually has a small number of general-purpose registers (e.g., thirty-two), and each register is usually the size of an integer.

Floating Point Registers
Processors that support floating point arithmetic often use a separate set of registers to hold floating point values.

Extended values
One of the most common arises if an instruction generates a large result, called an extended value. For example, integer multiplication can produce a result that contains twice as many bits as either operand. Some processors offer facilities for double precision arithmetic (e.g., if a standard integer is thirty-two bits wide, a double precision integer occupies sixty-four bits).
To handle extended values, the hardware treats registers as consecutive. On such processors, for example, an instruction that loads a double precision integer into register 4 will place half the integer in register 4 and the other half in register 5 (i.e., the value of register 5 will change even though the instruction contains no explicit reference). When choosing registers to use, a programmer must plan for instructions that place extended data values in consecutive registers.

Register Banks
An additional hardware detail complicates register allocation: some architectures divide registers into multiple banks, and require the operands for an instruction to come from separate banks.

Complex and Reduced Instruction Sets
Complex Instruction Set Computer (CISC)
Reduced Instruction Set Computer (RISC)

In contrast to CISC, a RISC processor is constrained. Instead of arbitrary instructions, a RISC design strives for a minimum set that is sufficient for all computation (e.g., thirty-two instructions). Instead of allowing a single instruction to compute an arbitrary function, each instruction performs a basic computation. To achieve the highest possible speed, RISC designs constrain instructions to be a fixed size. Finally, as the next section explains, a RISC processor is designed to execute an instruction in one clock cycle. Arm Limited and MIPS Corporation have each created RISC architectures with limited instructions that can be executed in one clock cycle.

Pipeline
Although a RISC processor cannot perform all steps of the fetch-execute cycle in a single clock cycle, an instruction pipeline with parallel hardware provides approximately the same performance: once the pipeline is full, one instruction completes on every clock cycle.

No-op instruction
Most processors include a no-op instruction that does not reference data values, compute a result, or otherwise affect the state of the computer. No-op instructions can be inserted to document locations where an instruction stall occurs.

An absolute branch computes a memory address, and the address specifies the location of the next instruction to execute. Typically, an absolute branch instruction is known as a jump.

Unlike an absolute branch instruction, a relative branch instruction does not specify an exact memory address. Instead, a relative branch computes a positive or negative increment for the program counter.

Most processors also provide an instruction to invoke a subroutine, typically jsr (jump subroutine). In terms of the fetch-execute cycle, a jsr instruction operates like a branch instruction with a key difference: before the branch occurs, the jsr instruction saves the value of the address register, A. When it finishes executing, a subroutine returns to the caller.

Register 0

One feature of the MIPS architecture, which is also used in other RISC processors, helps achieve minimalism: fast access to a zero value. In the case of MIPS, register 0 provides the mechanism — the register is reserved and always contains the value zero. Thus, to test whether a register is zero, the value can be compared to register zero. Similarly, register zero can be used in any instruction. For example, to copy a value from one register to another, an add instruction can be used in which one of the two operands is register zero.