6位数码管全显示为1时（片选信号SEL扫描）:
display
module display0(clk,reset_n,select,segment,clk_slow);
input clk;
input reset_n;
output reg [5:0] select;
output wire [7:0] segment;
output clk_slow;
reg [15:0] counter;
reg clk_slow;
//计数模块
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
counter <= 0;
else
counter <= counter + 16'b1;
end
//分频模块
always @(posedge clk)
begin
clk_slow <= counter[10];
end
//分配单个数码管上的显示模式
assign segment = 8'b11111001;
//扫描
always @(posedge clk_slow or negedge reset_n)
begin
if (!reset_n)
select <= 0;
else if(select == 6'b000_000)
select <= 6'b000_001;
else if(select == 6'b100_000)
select <= 6'b000_001;
else
select <= select<<1;
end
endmodule
值得注意:这里并不是数码管一个接一个的亮，而是同一时刻只有6位数码管中只有一位管子灭，其他均亮【把时钟放慢可以看出板子上的效果】
Testbench:
`timescale 1 ns/ 1 ps
module display0_vlg_tst();
reg clk;
reg reset_n;
wire [7:0] segment;
wire [5:0] select;
wire clk_slow;
display0 i1 (
.clk(clk),
.reset_n(reset_n),
.segment(segment),
.select(select),
.clk_slow(clk_slow)
);
initial
begin
clk = 1'b1;
reset_n = 1'b0;
#200 reset_n = 1'b1;
#10_000_000 $stop;
end
always #10 clk <= ~clk;
endmodule
6位数码管显示为“654321”时（片选信号SEL扫描+数码管信号SEG根据SEL进行变化）:
module display1(clk,reset_n,select,segment,clk_slow);
input clk;
input reset_n;
output wire [5:0] select;
output reg [7:0] segment;
output clk_slow;
reg [16:0] counter;
reg clk_slow;
reg [5:0] temp_select;
//计数模块
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
counter <= 0;
else
counter <= counter + 16'b1;
end
//分频模块
always @(posedge clk)
begin
clk_slow <= counter[12];
end
//分配单个数码管上的显示模式
//assign segment = 8'b11111001;
always @(*)//posedge select
begin
if(!reset_n)
segment <= 8'b11111111;
else
begin
case(temp_select)
6'b000_001:segment <= 8'b1111_1001;
6'b000_010:segment <= 8'b1010_0100;
6'b000_100:segment <= 8'b1011_0000;
6'b001_000:segment <= 8'b1001_1001;
6'b010_000:segment <= 8'b1001_0010;
6'b100_000:segment <= 8'b1000_0010;
default: segment <= 8'b1111_0000;
endcase
end
end
//扫描
always @(posedge clk_slow or negedge reset_n)
begin
if (!reset_n)
temp_select <= 0;
else if(temp_select == 6'b000_000)
temp_select <= 6'b000_001;
else if(temp_select == 6'b100_000)
temp_select <= 6'b000_001;
else
temp_select <= temp_select<<1;
end
assign select = ~temp_select;
endmodule
Testbench:
`timescale 1 ns/ 1 ps
module display0_vlg_tst();
reg clk;
reg reset_n;
wire [7:0] segment;
wire [5:0] select;
wire clk_slow;
display1 i1 (
.clk(clk),
.reset_n(reset_n),
.segment(segment),
.select(select),
.clk_slow(clk_slow)
);
initial
begin
clk = 1'b1;
reset_n = 1'b0;
#200 reset_n = 1'b1;
#10_000_000 $stop;
end
always #10 clk <= ~clk;
endmodule
